Agenda
14:00 Welcome Session and Keynote
14:00 Daniel Müller-Gritschneder (TU Wien), Willibald Krenn (SAL): Welcome
14:20 Herbert Taucher (Siemens): RISC-V in Industry – State of the Union
14:40 Philipp Tomsich (VRULL): Convergence for Embedded, HPC, and AI/ML:
Standards Initiatives for Matrix Processing Instructions in RISC-V
15:15 Academic Session
15:15 Stefan Mangard (TU Graz) - TBA
15:30 Daniel Große (JKU Linz): Mastering Early System Evaluation and Verification for RISC-V Vector
15:45 Markus Kobelrausch (TU Wien): A Methodology for Automating the Integration of User-Defined Instructions into RISC-V Systems based on the CV-X-IF Interface
16:00 Coffee Break
16:30 Industrial Session
16:30 Thomas Röcker (Infineon) - TBA
16:45 Marcus Borrmann (NXP): RISC-V landscape for NXP in Austria
17:00 Deepak V Katkoria ( LogiicDev) - TBA
17:15 Moderated Discussion - Towards a Roadmap for RISC-V in Austria
18:00 Networking and Drinks
Registration: A brief confirmation of your participation by mail to: edeltraud.sommer@tuwien.ac.at is appreciated.